The present invention relates to an apparatus for and a method of providing a clock signal for testing a device.
Semiconductor memories are used to store information in computer systems. As processor speeds continue to increase, the capacity and data rate of memory devices also continues to increase. Typically the processor accesses data at a much higher data rate than the data rate of the memories. In a memory system, a memory controller provides an interface between the memories and the processor. The memory controller and memories are designed to operate in accordance with predefined specifications. During the manufacturing process, the memory controller and memories are tested to ensure that they operate in accordance with the specifications. For example, the memory controller has inputs or pins that transmit and receive external clock signals, control signals and data signals. To test the memory controller, the memory controller is placed in a socket at a test station and the external clock signal and data signals are supplied, varied, and the performance of the memory controller is measured. As data rates increase, the frequency of the external clock signal increases. Supplying an external high speed clock requires an expensive high speed tester. Memory controllers are becoming increasingly sophisticated and may provide an internal high speed clock signal. Therefore, to reduce cost and simplify testing, an apparatus and method that uses the internal high speed clock for testing the memory controller is needed.
In summary, the present invention provides a clock signal driven device that has a clock pin for receiving an externally generated clock signal during a normal mode of operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during the normal mode of operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device""s internal circuitry is responsive to the test clock signal during the test mode of operation.
In a preferred embodiment, the device has two clock pins that receive externally generated differential clock signals, and the internal clock generator generates a pair of differential test clock signals that are asserted on the two clock pins. A set of clock current control bits are stored in a register. The internal clock generator includes a plurality of clock output drivers for generating each test clock signal, with each of the clock output drivers being selectively enabled by a corresponding one of the clock current control bits. Each clock output driver preferably includes a slew rate controlled predrive circuit that generates an intermediate clock signal having a slew rate in accordance with a set of slew rate control bits stored in a slew rate control register.